CHIPSAlliance

The whitepaper is here! Designed to demystify the current state of #openhardware #opensilicon, outline the challenges ahead, and chart a path forward for everyone from startups to silicon giants. chipsalliance.org/news/tac-white…

Topwrap is an open source toolkit for creating machine- and human-readable top level designs, w/ reusable user-defined repositories, automatic interconnect generation & an enhanced interface grouping mechanism: chipsalliance.org/news/topwrap/ @antmicro @risc_v @linuxfoundation

In space no one can hear your hardware beep. See how simulation in @renodeio lets you scalably develop & test complex, heterogeneous #ASIC & #FPGA-based systems that can last decades outside Earth's atmosphere w/o taking years to build: antmicro.com/blog/2024/02/d… @risc_v #opensource

The first-ever CHIPS Alliance newsletter is live! Check it out for the latest community updates. 👍 Like if you're building open source silicon 🔁 Share to connect more developers to the ecosystem 💬 Drop a comment if you have updates or news to share linkedin.com/pulse/q2-chips…

What does a collaborative open source chip design environment look like? At DAC, CHIPS Alliance’s Robert Mains moderates a session on open ISAs, PDKs, EDA, cloud-based design, & Caliptra. 📅 June 25 | ⏰ 10:30am 🔗 hubs.la/Q03rWpqL0 #DAC2025 #CHIPSAlliance #OpenHardware

What does a collaborative open source chip design environment look like? At DAC, CHIPS Alliance’s Robert Mains moderates a session on open ISAs, PDKs, EDA, cloud-based design, & Caliptra. 📅 June 25 | ⏰ 10:30am 🔗 hubs.la/Q03r528_0 #DAC2025 #CHIPSAlliance #OpenHardware

New Blog: Interactive #RTL Coverage Dashboards for #VeeR and #Caliptra. In this post, @antmicro walks through how Coverview is used to track verification for the VeeR EL2 core, part of the Caliptra project. chipsalliance.org/news/coverage-…

New revision of Antmicro's highly popular Open Source Jetson Orin Baseboard is back in stock at @CircuitHub. Same small footprint with support for both @Nvidia Jetson Orin Nano and NX SoMs in Super mode for an extra edge AI compute boost order.openhardware.antmicro.com

Come check out the #Caliptra Root of Trust demo booth A13 courtesy of #AMI at @OpenComputePrj EMEA Summit #Dublin.

Heading to the @OpenComputePrj 2025 EMEA Summit? Don’t miss this talk... Caliptra – Subsystem Firmware Stack Wednesday, April 30 · 9:50 AM Level 1 - Liffey Hall 2 #Caliptra #OCP2025 #CHIPSAlliance #OpenSourceSilicon #FirmwareSecurity

Heading to @OpenComputePrj #OCPEMEA next week? 🔹 Meet CHIPS Alliance ED Rob Mains at Booth A13 🔹 Catch Caliptra firmware stack talk – April 30, 09:50, Liffey Hall 2 🔹 Explore open source silicon + system design with us! #Caliptra #OpenCompute #OpenSourceSilicon

Read about @antmicro's further developments towards Caliptra 2.0 RoT: support for the @risc_v VeeR EL2 core w/ User mode and PMP in the embedded Tock OS: chipsalliance.org/news/caliptra-… @talkingtock @AMD @Google @Microsoft @nvidia

Meet us at #RISCVSummit this week to learn about @risc_v and @CHIPSAlliance collaboration and the synergies offered by the open ISA and open silicon/hardware design in projects like #Caliptra RoT @amd @google @microsoft @nvidia @linuxfoundation events.linuxfoundation.org/riscv-summit/

The interplay between hardware and software is a critical part of designing next-gen chips for e.g. AI and HPC. Join @CHIPSAlliance, @OpenPOWERorg and @RISC_V at this co-located #OSSummit event for industry insight on the current open source landscape. events.linuxfoundation.org/open-source-su…

At #OSSummit Vienna, we will be giving a talk on @CHIPSAlliance #Caliptra 2.0 led by @AMD @Google @Microsoft @NVIDIA. We will examine enhancing the @risc_v #VeeR EL2 core with #I3C, U-mode, and enabling open source verification: events.linuxfoundation.org/open-source-su… @LF_Europe @OpenPOWERorg

The interplay between hardware and software is a critical part of designing next-gen chips for e.g. AI and HPC. Join @CHIPSAlliance, @OpenPOWERorg and @RISC_V at this co-located #OSSummit event for industry insight on the current open source landscape. events.linuxfoundation.org/open-source-su…

CHIPS Alliance is a mentor organization at this year's @Google Summer of Code! Join our mission to push forward #opensource #hardware, #ASIC & #FPGA design. Check out our project ideas & apply by April 2: github.com/chipsalliance/… @GoogleOSS @antmicro @risc_v @f4pga @OpenROAD_EDA

This year at #OSSummit in Seattle, @risc_v, @OpenPOWERorg and @CHIPSAlliance are teaming up for a mini summit! Join us on April 15 to hear from speakers from @Microsoft, @intel, @awscloud, @antmicro, @RedHat, @Codasip, @uoregon and @linuxfoundation: events.linuxfoundation.org/open-source-su…

As #Rowhammer continues to be a serious threat for DRAM technologies, @antmicro released a SO-DIMM (LP)DDR5 testing platform with PCIe, adding to the #opensource FPGA-based testing suite developed for @Google. Learn more: chipsalliance.org/news/versatile… @AMDembedded

Get more insight to verilation processes and ASTs with astsee, @antmicro's #opensource toolkit for pretty-printing, diffing, and exploring ASTs from a wide range of sources including #Verilator. Learn more: chipsalliance.org/news/analyze-v… #fpga #asic #json