Isil Dillig
@IsilDillig
CS Professor at UT Austin + President of @VeridiseInc.
Thank you @swarat! I’m very honored to receive this award
Just learned that @IsilDillig won the #SIGPLAN Robin Milner Junior researcher award this year! 🎈 🍾 The award goes to one outstanding mid-career PL researcher each year, and it’s hard to think of a more deserving candidate for it. Congratulations, Isil! sigplan.org/Awards/Milner/
The United States has had a tremendous advantage in science and technology because it has been the consensus gathering point: the best students worldwide want to study and work in the US because that is where the best students are studying and working. 1/
It's been a real honor and privilege to be your PhD advisor @ShankaraPailoo2 and Ben Mariano! I am truly so proud of everything you both have accomplished.
The FY26 budget slashes NSF by 55%, which directly threatens basic research in the United States. Please call your reps NOW and tell them to reject these cuts and protect science funding. You can find them here : congress.gov/members
For folks interested in C-to-Rust translation, we put together a benchmark suite you can evaluate on!
🚀Introducing CRUST-Bench, a dataset for C-to-Rust transpilation for full codebases 🛠️ A dataset of 100 real-world C repositories across various domains, each paired with: 🦀 Handwritten safe Rust interfaces. 🧪 Rust test cases to validate correctness. 🧵[1/6]
Check out this really cool work led by my brilliant student @divytweet on novel control and data plane abstractions for service meshes! With @isildillig
Presented our work on programming service mesh policies at low overheads at @ASPLOSConf! We propose two novel abstractions that allow using diverse dataplanes and simplify policy expression for request paths in microservice networks.
Thank you for your kind words for our team @BruestleJeremy! It’s been a pleasure to work with the @RiscZero team.
⭐ 🎥 Watch a 7-min chat with @RiscZero CEO @BruestleJeremy on his founding journey, RISC Zero's security priorities, and his experience with @VeridiseInc.
RISC Zero is building the first formally verified RISC-V zkVM. Using @VeridiseInc's Picus tool, we're mathematically proving determinism in our circuits. Our goal: A zkVM that’s both incredibly fast and provably secure, so developers never have to compromise.
For formal methods folks looking for a new position: @VeridiseInc is hiring a formal methods researcher to work on verification/analysis tools targeting zero-knowledge applications. More details are here: veridise.com/careers/zk-res…
PSA for PL folks on this platform: We now exist on another platform, please join. Here is a starter pack with a whole bunch of us: bsky.app/starter-pack-s…
Really hope more people migrate to this platform soon: nytimes.com/2024/11/12/sty…
For my sanity, I intend to be off this platform for a while. For those on bluesky or plan to join, this is me: bsky.app/profile/idilli…
Great interview with @ShankaraPailoo2!
New blog post is live: "Meet Our Team: 10 questions for Shankara Pailoor" @mikkoikola sat down with our Head of ZK Security Research @ShankaraPailoo2 to discuss everything from Shankara's PhD journey, best practices for secure ZK development, Picus tool, to philosophy! Find the…
For those reaching out to me for the upcoming PhD admissions cycle: Yes, I am taking students and post-docs with a strong PL background and similar research interests. So, if you are interested, please apply to UTCS!